PARTNO	  XXXXX ;
		NAME	  U112;
		DATE	  November 8, 1988;
		REV	  2;
		DESIGNER  Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  BIGRAM ;
		LOCATION  U112;

/************************************************************************/
/*									*/
/*  BIGRAM	RAS and burst generation machine			*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 16R4B 				*/
/************************************************************************/
/*  Free Pins: 14(Q)							*/
/************************************************************************/
/*  HISTORY							  	*/
/*	DBH Oct  3:	Created from A2630's U600R7			*/
/************************************************************************/

/**  Inputs **/ 

PIN 2		= !ASDELAY	;	/* AS plus arbitration delay */
PIN 3		= !AS		;	/* 68030 address strobe */
PIN 4		= !OE3		;	/* Output enable for last bank */
PIN 5		= !REFACK	;	/* It's a refresh cycle */
PIN 6		= !BGACK	;	/* Bus grant acknowledge */
PIN 7		= !CBREQ	;	/* Cache burst request */
PIN 8		= !SLOW		;	/* Delay for cache bursts? */
PIN 9		= !MEMSEL	;	/* The CPU is accessing our RAM */
PIN 12		= !STERMDLY	;	/* Delay for starting STERM */
PIN 13		= !ROFF		;	/* RAS off qualifier, help meet Trp */

/**  Outputs **/

PIN 19		= !RASEN	;	/* Cycle RAS enable */
PIN 18		= !CBACK	;	/* Cache burst acknowledge */
PIN 17		= !STERM	;	/* Synchronous cycle terminator */

/**  Used internally */

PIN 15		= !SDEL		;	/* STERM delay in SLOW mode */
PIN 16		= !CBQ		;	/* Delayed burst request */

/** Declarations and Intermediate Variable Definitions **/

/* The standard qualification for a CPU memory cycle.  We have to wait
   until refresh is arbitrated, and make sure it's really our cycle. */

cpucycle	= !REFACK & MEMSEL & ASDELAY &  AS;

/* This is the delayed version of CBREQ used to properly arbitrate 
   the CBACK line and it's application in the read strobe counter.  */

CBQ.D		= CBREQ;

/* This is the STERM delay used in SLOW mode. */

SDEL.D		= cpucycle & STERMDLY;

/* This is the basic RAS enable.  If you haven't acknowledged refresh
   and the memory is being selected, RAS goes on address strobe.  We
   take care of refresh elsewhere. */

RASEN		= cpucycle & !ROFF 
		# cpucycle & RASEN & !CBACK
		# cpucycle & RASEN &  CBACK & CBREQ;

/* This is the burst acknowledge signal.  We want to acknowledge burst
   for any on-board DRAM cycles.  It's important to have a finite delay 
   between CBACK and CBREQ so that the output enable terms can get 
   started OK. */

CBACK		= MEMSEL & AS &   CBQ
		# MEMSEL & AS & CBACK & !STERM;
CBACK.OE	= MEMSEL;

/* This is the cycle termination term.  There are basically two parts to
   it.  First of all, we always need to start an STERM for any memory
   access, pretty much as normal.  Then we have to handle bursting.  If
   there's no burst delay, we stay low as long as there's a burst state.
   If there is a burst delay, we bring STERM alternately high and low. */

STERM.D		= cpucycle & STERMDLY & !SLOW & !CBACK & !STERM
		# cpucycle & STERMDLY & !SLOW &  CBACK
		# cpucycle &    STERM & !SLOW &  CBACK
		# cpucycle &     SDEL &  SLOW & !STERM;