PARTNO	  XXXXX ;
		NAME	  U107;
		DATE	  November 8, 1988;
 		REV	  3 ;
		DESIGNER  Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  BIGRAM ;
		LOCATION  U107 ;

/************************************************************************/
/*									*/
/*  BIGRAM 	DRAM Output and Write Enable Generation			*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 20R4B 				*/
/************************************************************************/
/*  Free Pins: 9(I),10(I),11(I)						*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Oct  3:	New, Based on U602R6 for A2630R3		*/
/*	DBH Oct  4:	Fixed MEMSEL polarity				*/
/*	DBH Nov  8:	Updated to reflect A2630 changes.		*/
/************************************************************************/

/**  Inputs  **/

PIN 2		=  MEMSEL	;	/* On-Board memory selected */
PIN 3		= !REFACK	;	/* Are we doing refresh? */
PIN 4		= !REFHOLD	;	/* Hold off till refresh is done */
PIN 5		= !STERM	;	/* Synchronous cycle termination */
PIN 6		=  RW		;	/* CPU Read/Write signal */
PIN 7		= !CBREQ	;	/* Cache burst request */
PIN 8		= !CBACK	;	/* Cache burst acknowledge */
PIN 14		=  A3		;	/* CPU address line */
PIN 23		=  A2		;	/* CPU address line */

/**  Outputs  **/

PIN 22		= !WE0		;	/* Lowest write strobe */
PIN 21		= !WE1		;
PIN 16		= !WE2		;
PIN 15		= !WE3		;	/* Highest write strobe */
PIN 20		= !OE0		;	/* Lowest output enable */
PIN 19		= !OE1		;
PIN 18		= !OE2		;
PIN 17		= !OE3		;	/* Highest output strobe */

/** Declarations and Intermediate Variable Definitions **/

/* Is this a burst cycle? */

burst		= CBACK;

/* The basic write cycle is concerned with memory selected during a
   non-refresh cycle.  */

writecycle	= !RW & MEMSEL & !REFHOLD & !REFACK;

/* The basic read cycle starts as simply as a write cycle.  It may be
   followed by up to three burst cycles. */

readcycle	=  RW & MEMSEL;

/* There are four memory banks of 32 bits each.  A two meg board will
   only support the upper two banks. */

bank0		=  !A2 & !A3;
bank1		=   A2 & !A3;
bank2 		=  !A2 &  A3;
bank3		=   A2 &  A3;

/** Logic Equations **/

/* The write strobes are not bursting strobes.  We basically just look at
   the address to pick the proper bank, and then let 'em rip.  */

WE0		= writecycle & bank0;
WE1		= writecycle & bank1;
WE2		= writecycle & bank2;
WE3		= writecycle & bank3;

/* The output enables, or read strobes, are bursting strobes.  The first
   read cycle will work just like the write cycle, and it assumes burst
   request isn't asserted.  That could be the end, but if we're in a 
   burst cycle, we go on to the next bank as soon as the current one gets
   it's STERM.  */

OE0.D		= !burst & readcycle & bank0 & !STERM
		#  burst & OE3 &  STERM & CBREQ
		#  burst & OE0 & !STERM;

OE1.D		= !burst & readcycle & bank1 & !STERM
		#  burst & OE0 &  STERM & CBREQ
		#  burst & OE1 & !STERM;

OE2.D		= !burst & readcycle & bank2 & !STERM
		#  burst & OE1 &  STERM & CBREQ
		#  burst & OE2 & !STERM;

OE3.D		= !burst & readcycle & bank3 & !STERM
		#  burst & OE2 &  STERM & CBREQ
		#  burst & OE3 & !STERM;