PARTNO	  XXXXX ;
		NAME	  U103 ;
		DATE	  October 4, 1988 ;
		REV	  2 ;
		DESIGNER  Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  BIGRAM ;
		LOCATION  U103 ;

/************************************************************************/
/*									*/
/*  BIGRAM 	DRAM RAS banking and CAS generation			*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 20L8B 				*/
/************************************************************************/
/*  Free Pins: NONE							*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Oct  3:	New, based on U603R1, from A2630R3		*/
/*	DBH Oct  4:	Fixed MEMSEL polarity				*/
/************************************************************************/

/**  Inputs  **/

PIN 1		= !REFCAS	;	/* Refresh CAS */
PIN 2		= !REFHOLD	;	/* CAS holdoff during refresh */ 
PIN [3..4]	=  [SIZ0..1]	;	/* CPU data size bits */
PIN 5		=  MEMSEL	;	/* Memory selected */
PIN 6		= !DS		;	/* CPU data strobe qualifier */
PIN 7		= !RASEN	;	/* General RAS enable */
PIN 8		= !REFRAS	;	/* Refresh RAS enable */
PIN 9		= !CAS		;	/* CAS enable */
PIN 10		=  A23		;	/* CPU addresses */
PIN 11		=  A22		;
PIN 14		=  A1		;
PIN 23		=  A0		;
PIN 13		=  RW		;	/* CPU R/W line */

/**  Outputs  **/

PIN 15		= !RAS0		;	/* RAS for bank 0 */
PIN 16		= !RAS1		;	/* RAS for bank 1 */
PIN 17		= !RAS2		;	/* RAS for bank 2 */
PIN 18		= !RAS3		;	/* RAS for bank 3 */
PIN 19		= !CAS0		;	/* CAS for byte 0 */
PIN 20		= !CAS1		;	/* CAS for byte 1 */
PIN 21		= !CAS2		;	/* CAS for byte 2 */
PIN 22		= !CAS3		;	/* CAS for byte 3 */

/** Declarations and Intermediate Variable Definitions **/

/* There are 4 banks of 4 megs each on board... */

bank0		= !A23 & !A22;

bank1		= !A23 &  A22;

bank2		=  A23 & !A22;

bank3		=  A23 &  A22;

/* We want CAS enabled when memory is selected and the CAS input from the
   delay line is asserted.  We want CAS off at the end of the cycle: DS
   or UDS/LDS will do the job here pretty well.  */

casen		= MEMSEL & CAS & !REFHOLD;

/* There are several conditions under which a particular byte is selected,
   based on the address on the bus and the size bits.  This is explained in
   the 68030 manual.  Additionally, this PAL will enable all bytes for a
   READ cycle, so that the '030 may properly use it's data cache on this 
   memory. */

byte0		= SIZ1 & SIZ0 & A0
		# !SIZ1 & !SIZ0
		# A1 & A0
		# SIZ1 & A1 ;

byte1		= A1 & !A0
		# !SIZ1 & !SIZ0 & !A1
		# !A1 & SIZ0 & SIZ1
		# A0 & !A1 & !SIZ0 ;
		   
byte2		= !SIZ0 & !A1
		# !A1 & A0
		# SIZ1 & !A1 ;

byte3		= !A1 & !A0 ;

/* The 68030 wants full port reads always for cachable memory. */

cpuread		= RW;

/**  Logic Equations  **/

/* The RAS lines select the proper 4 meg bank out of the 16 meg of
   memory, and we all refresh together. */

RAS0		= RASEN & bank0
		# REFRAS;

RAS1		= RASEN & bank1
		# REFRAS;

RAS2		= RASEN & bank2
		# REFRAS;

RAS3		= RASEN & bank3
		# REFRAS;

/* The CAS lines select the proper byte out of a longword. */

CAS0		= casen & DS &   byte0
		# casen & DS & cpuread
	 	# REFCAS;

CAS1	 	= casen & DS &   byte1
	 	# casen & DS & cpuread
	 	# REFCAS;

CAS2	 	= casen & DS &   byte2
	 	# casen & DS & cpuread
	 	# REFCAS;

CAS3	 	= casen & DS &   byte3
	 	# casen & DS & cpuread
	 	# REFCAS;