PARTNO XXXXX ; NAME U100; DATE October 5, 1988 ; REV 2 ; DESIGNER Haynie ; COMPANY Commodore ; ASSEMBLY BIGRAM ; LOCATION U100 ; /************************************************************************/ /* */ /* BIGRAM Decoding and Buffer Logic */ /* */ /************************************************************************/ /* Allowable Target Device Types: 16L8B */ /************************************************************************/ /* Free Pins: 8(I),9(I),16(IO),17(IO),18(IO) */ /************************************************************************/ /* HISTORY */ /* DBH Oct 3: Newly created for BIGRAM Rev 2 */ /* DBH Oct 5: Fixed D2P polarity */ /************************************************************************/ /** Inputs **/ PIN 1 = !AS ; /* CPU Address strobe */ PIN 2 = FC0 ; /* CPU Function Codes */ PIN 3 = FC1 ; PIN 4 = FC2 ; PIN 5 = RW ; /* CPU Read/Write strobe */ PIN 6 = PMX ; /* Pre-MUX Signal */ PIN 7 = !BGACK ; /* DMA device is bus master */ PIN 11 = A24 ; /* High order address bit */ /** Outputs **/ PIN 19 = !MEMSELN ; /* Active low board select */ PIN 15 = MUX ; /* DRAM address multiplexer */ PIN 14 = !DBOE ; /* Data buffer enable */ PIN 13 = !D2P ; /* Data direction toward CPU */ PIN 12 = MEMSELP ; /* Active high board select */ /** Declarations and Intermediate Variable Definitions **/ cpuspace = FC0 & FC1 & FC2; memcycle = !cpuspace & !BGACK & A24; /** Logic Equations **/ /* All we do here is create a buffered MUX, just 'cause there wasn't a buffer leftover. */ MUX = PMX; /* Memory is selected whenever we're a high-order address and not in cpuspace or being DMAed. */ MEMSELP = memcycle; MEMSELN = memcycle; /* Data direction control is really simple. If we're selected, and it's a read cycle, the buffers point thatta way, otherwise they point thissa way. */ D2P = memcycle & RW; /* Data output enable is similarly pretty simple. We just want to be enabled when we're selected. */ DBOE = memcycle & AS;