PARTNO	  390287-01 ;
		NAME	  U601;
		DATE	  July 25, 1988;
		REV	  8 ;
		DESIGNER  Welland/Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  312828 ;
		LOCATION  U601;

/******************************************************************/
/*								  */
/*  68020 MMU	Refresh state machine.				  */
/*								  */
/******************************************************************/
/*  Allowable Target Device Types: 16R8A (390070-01)		  */
/******************************************************************/
/*  Free Pins: 5-9(I)						  */
/******************************************************************/
/*  HISTORY							  */
/*	DBH Dec 23:	Found RRASEN is currently unused	  */
/*	DBH Jul 25:	Added HOLD term to prevent invalid CAS	  */
/*			after refresh cycles.			  */
/******************************************************************/

/**  Inputs  **/

PIN 2	     = !EREFREQ  ;	/* Unsynchronised refresh request */
PIN 3	     = !REFACK	 ;	/* Refresh request acknowledge */
PIN 4	     = !DELCAS	 ;	/* Basis for external CAS */

/**  Outputs  **/

PIN 16	     = !HOLD	 ;	/* Holdoff during refresh (REFHOLD) */
PIN 17	     = !ICAS	 ;	/* Refresh CAS control (REFCAS) */
PIN 18	     = !IRAS	 ;	/* Raw RAS output */
PIN 19	     = !WANT	 ;	/* We want to bus to do refresh */

/**  Used Internally **/

PIN 15	     = !IREFREQ  ;	/* Synchronised refresh request */
PIN 12	     = !StBit2	 ;	/* State bit 2 */
PIN 13	     = !StBit1	 ;	/* State bit 1 */
PIN 14	     = !StBit0	 ;	/* State bit 0 */


/** Declarations and Intermediate Variable Definitions **/

/**  Logic Equations  **/

/* This is the internal refresh request, which is basically a
   synchronized version of the external refresh request. */

IREFREQ.D =	EREFREQ
	  #	IREFREQ & !REFACK;

/* This is the refresh cycle state counter. */

StBit2.D =	( IREFREQ & !StBit0 & !StBit2)
	#	( !REFACK & !StBit0 & !StBit1 & StBit2)
	#	( StBit0 & !StBit1 & !StBit2)
	#	( !StBit0 & StBit1 & !StBit2);
StBit1.D =	( REFACK & !StBit0 & !StBit1 & StBit2)
	#	( StBit0 & !StBit1 & StBit2)
	#	( !StBit0 & StBit1 & !StBit2);
StBit0.D =	( StBit0 & !StBit1 & !StBit2)
	#	( StBit0 & !StBit1 & StBit2)
	#	( !StBit0 & StBit1 & StBit2);

/* This is the refresh machine's refresh request. */

WANT.D =	( IREFREQ & !StBit0 & !StBit2)
	#	( REFACK & !StBit0 & !StBit1 & StBit2)
	#	( !REFACK & !StBit0 & !StBit1 & StBit2)
	#	( StBit0 & !StBit1 & !StBit2)
	#	( StBit0 & !StBit1 & StBit2)
	#	( !StBit0 & StBit1 & !StBit2)
	#	( !StBit0 & StBit1 & StBit2);

/* This drives RAS for a refresh cycle */

IRAS.D = 	( !StBit0 & StBit1 & !StBit2)
	#	( !StBit0 & StBit1 & StBit2);

/* This drives CAS for a refresh cycle */

ICAS.D = 	( REFACK & !StBit0 & !StBit1 & StBit2)
	#	( !StBit0 & StBit1 & !StBit2)
	#	( !StBit0 & StBit1 & StBit2);

/* This holds off any real CAS cycles until the refresh cycle is
   completely over.  The problem this fixes is that when refresh
   happens during a memory cycle, the CAS PAL will generate CAS for
   a refresh cycle, as it's supposed to, but may right after that
   generate a second CAS.  This second CAS can go low before the
   refresh RAS goes high, and if this happens, a memory glitch is
   just about certain to happen.  So, this allows the CAS PAL to
   know that a refresh cycle is fully over with before allowing any
   normal CAS to occur.  Note that this glitch has never shown up
   in a standard A2620 board, but it has in faster lab versions,
   so this is basically just a precaution here. */

HOLD.D	= ICAS 
	# HOLD & IRAS
	# HOLD & DELCAS ;