PARTNO	  390295-01 ;
		NAME	  U600 ;
		DATE	  August 16, 1988;
		REV	  18 ;
		DESIGNER  Welland/Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  312828 ;
		LOCATION  U600 ;

/******************************************************************/
/*								  */
/*  68020 MMU	Refresh arbitration logic			  */
/*								  */
/******************************************************************/
/*  Allowable Target Device Types: 20R4B (390327-01)		  */
/******************************************************************/
/*  Free Pins: 8(I), 10(I), 17(Q)				  */
/******************************************************************/
/*  HISTORY							  */
/*	DBH Dec 23:	DMADSACK goes away!			  */
/*	DBH Dec 23:	Modified RAS stuff for 4 Meg operation	  */
/*	DBH Dec 23:	Added A21 for RAS arbitration		  */
/*	DBH Dec 23:	Moved DMA R/W generation to U505	  */
/*	DBH Feb 23:	Changed A21 to !BANK for bank selection   */
/*	DBH Feb 25:	Yet again fixed 2/4 meg stuff re !BANK	  */
/*	DBH May  7:	Added ROFF to ensure TRP with short cycle */
/*	DBH Jul 13:	Moved BANK pin to reflect new PCB	  */
/*	DBH Aug 16:	Removed ROFF term due to MMU conflict	  */
/******************************************************************/

/**  Inputs **/ 

PIN 2	     = !AS	 ;	/* 68851 address strobe */
PIN 3	     = !AAS	 ;	/* Amiga bus address strobe */
PIN 4	     = !BGACK	 ;	/* Bus grant acknowledge */
PIN 5	     = !WANT	 ;	/* Refresh wants the bus */
PIN 6	     = !MEMSEL	 ;	/* The CPU is accessing our RAM */
PIN 7	     = !IRAS	 ;	/* Raw Ras output */
PIN 9	     = !ASDELAY  ;	/* Address strobe delayed 20ns */
PIN 8	     = !BANK	 ;	/* Address line for RAS bank select */
PIN 14	     = !ROFF	 ;	/* Turns off RAS to ensure TRP */

/**  Outputs related to refresh arbitration **/

PIN 22	     = !DSACKEN  ;	/* Enable DSACKx for this RAM cycle */
PIN 21	     = !RASEN	 ;	/* RAS is going for either bank */
PIN 20	     = !REFACK	 ;	/* Refresh request acknowledge */
PIN 16	     = !RASEN0	 ;	/* RAS generation for the first 2Megs */
PIN 15	     = !RASEN1	 ;	/* RAS generation for the second 2Megs */

/**  Used Internally **/

PIN 19	     = !AASP	 ;	/* AAS Prime */
PIN 18	     = !AASPP	 ;	/* AAS Prime^2 */

/** Declarations and Intermediate Variable Definitions **/

/**  Logic Equations related to the refresh arbitration logic **/

/* These next two synchronized versions of AS are to ensure that the
   refresh arbitration during DMA works properly, by syncing the 
   external address strobe to the internal clock. */

AASP.D	 = AAS ;

AASPP.D	 = AASP ;

/* This is the refresh acknowledge, which only gets asserted when a
   refresh request (WANT) has been asserted.  A refresh request can
   be acknowledged in a number of cases.  If the 68020 is in charge
   and you`re not running a cycle, it's OK to refresh.  If the 68020
   is in charge and you're running a cycle, but not to on-board memory,
   its also OK.  If it's a DMA cycle, similar treatment is given, only
   using the synchronized AAS.  The final term is a holding term to 
   keep this signal asserted as long as WANT is valid. */

REFACK.D = (WANT & !AS & !BGACK)
	 # (WANT & AS & !MEMSEL & !BGACK)
	 # (WANT & !AASP & BGACK)
	 # (WANT & AASP & !MEMSEL & BGACK)
	 # (WANT & REFACK);

/* This is the basic RAS enable.  If you haven't acknowledged refresh
   and the memory is being selected by the 68020, RAS goes on address
   strobe.  If it's a DMA cycle, RAS goes on the delayed synced Amiga
   address strobe.  And if it`s a DMA cycle, go.  */

RASEN	 = !REFACK & MEMSEL & AS & ASDELAY & !BGACK
	 # !REFACK & MEMSEL & AASPP & BGACK
	 # IRAS;

/* Bank-related RAS enables are very similar to the above RAS enable,
   only the bank term is added in.  If it's a memory access cycle,
   you only assert RASEN0 on !BANK, and RASEN1 on BANK.  If it's a
   refresh cycle, both should go based on IRAS. */

RASEN0	 = !REFACK & MEMSEL & AS & ASDELAY & !BGACK & !BANK
	 # !REFACK & MEMSEL & AASPP & AAS & BGACK & !BANK
	 # IRAS ;

RASEN1	 = !REFACK & MEMSEL & AS & ASDELAY & !BGACK & BANK
	 # !REFACK & MEMSEL & AASPP & AAS & BGACK & BANK
	 # IRAS ;

/* This generates DSACK for the DRAM, which works just like the above
   enables for RAS, only refresh isn't considered (of course). */

DSACKEN  = !REFACK & MEMSEL & AS & ASDELAY & !BGACK #
	   !REFACK & MEMSEL & AASP & AAS & BGACK ;