PARTNO	  390284-01 ;
		NAME	  U505;
		DATE	  Dec 23, 1987;
		REV	  7 ;
		DESIGNER  Welland/Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  312828 ;
		LOCATION  U505;

/******************************************************************/
/*								  */
/*  68020 MMU	Amiga bus cycle control and refresh cycle control */
/*								  */
/******************************************************************/
/*  Allowable Target Device Types: 16R4B (390328-01)		  */
/******************************************************************/
/*  Free Pins: 12(I/O)						  */
/******************************************************************/
/*  HISTORY							  */
/*	DBH Dec 23:	Added DMA R/W generation from U600	  */
/*	DBH Dec 23:	Moved into 16R6 from 20R6 package	  */
/******************************************************************/

/**  Inputs  **/

PIN 2	     = !ASEN	 ;	/* Adress strobe enable */
PIN 3	     = !DTACK	 ;	/* The Amiga Data transfer acknowledge */
PIN 4	     = !EDTACK	 ;	/* DTACK for a 6800 cycle */
PIN 5	     = !ONBOARD  ;	/* An onboard device cycle */
PIN 6	     = !AS	 ;	/* Adress strobe */
PIN 7	     = !BGACK	 ;	/* Bus grant acknowledge */
PIN 8	     = ARW	 ;	/* DMA R/W line */

/**  Outputs  **/

PIN 19	     = !DSACKDIS ;	/* DSACK disable */
PIN 18	     = !S7MDIS	 ;	/* Disable the S7M clock */
PIN 17	     = DSEN	 ;	/* Data strobe enable */
PIN 16	     = !DSACKEN  ;	/* DSACK enable */
PIN 15	     = CYCEND	 ;	/* End of cycle */
PIN 14	     = S_7MDIS   ;	/* Disable the S_7M clock */
PIN 13	     = PRW	 ;	/* 68020 Read/Write - routed only during DMA */

/** Declarations and Intermediate Variable Definitions **/


/**  Logic Equations  **/

DSACKDIS = !AS;
S7MDIS = (!DSEN & ASEN & DSACKEN);
S_7MDIS.D = (ASEN & CYCEND);
!DSEN.D  = (ASEN & CYCEND);
!DSACKEN.D = (!DSEN & CYCEND & DTACK)
	  # (!DSEN & CYCEND & EDTACK)
	  # (!DSEN & CYCEND & ONBOARD);
!CYCEND.D = (!DSACKEN & CYCEND);

/** Logic Equations related to the DMA to RAM interface **/

PRW	 = ARW;
PRW.OE = BGACK;