PARTNO	  390294-01 ;
		NAME	  U504 ;
		DATE	  July 25, 1988 ;
		REV	  6 ;
		DESIGNER  Haynie/Welland ;
		COMPANY   Commodore ;
		ASSEMBLY  312828 ;
		LOCATION  U504 ;

/******************************************************************/
/*								  */
/*  68020 MMU	DRAM CAS generation				  */
/*								  */
/******************************************************************/
/*  Allowable Target Device Types: 20L8A (390325-01)		  */
/******************************************************************/
/*  Free Pins: NONE						  */
/******************************************************************/
/*  HISTORY							  */
/*	DBH Jul 25:	Added REFHOLD refresh cycle qualifier	  */
/*	DBH Jul 25:	Removed RAS from "casen" equation	  */
/******************************************************************/

/**  Inputs  **/

PIN 1		= !CAS		; 	/* CAS enable */ 
PIN 2		= !UDS		;	/* Upper Data strobe */
PIN 3		= !LDS		;	/* Lower Data strobe */
PIN [4..5]	= [SIZ0..1]	;	/* Data size bits */
PIN [6..7]	= [A0..1]	;	/* Adress lines 0-1 */
PIN 8		= !BGACK	;	/* Bus grant acknowledge */ 
PIN 9		= !REFCAS	;	/* Early CAS for refresh cycle */
PIN 10		= !MEMSEL	;	/* Memory selected */
PIN 11		= !RAS		;	/* RAS qualifier */
PIN 13		= !REFHOLD	;	/* CASE holdoff during refresh */
PIN 14		= HIGH		;	/* High bank qualifier */
PIN 23		= !DS		;	/* Data strobe qualifier */

/**  Outputs  **/

PIN 15	     = !CAS0LL	 ;	/* CAS line */
PIN 16	     = !CAS0LH	 ;	/* CAS line */
PIN 17	     = !CAS0HL	 ;	/* CAS line */
PIN 18	     = !CAS0HH	 ;	/* CAS line */
PIN 19	     = !CAS1LL	 ;	/* CAS line */
PIN 20	     = !CAS1LH	 ;	/* CAS line */
PIN 21	     = !CAS1HL	 ;	/* CAS line */
PIN 22	     = !CAS1HH	 ;	/* CAS line */

/** Declarations and Intermediate Variable Definitions **/

/* CAS will be enabled for a normal cycle when memory is selected,
   the CAS tap input is valid, and we're not in a refresh cycle.
   The CAS term will be cut off by the proper data strobe signal
   later on. */

casen	= MEMSEL & CAS & !REFHOLD ;

/* These terms allow selection of the appropriate bank of RAM; there
   are two banks CAS multiplexed and two banks RAS multiplexed on
   the 4 meg system. */

lowen	= casen & !HIGH	;
highen	= casen & HIGH ;

/* These are the byte select terms for each of the four bytes in a
   longword.  There are several conditions under which a particular byte 
   is selected, based on the address on the bus and the size bits.  This 
   is explained in the 68020 manual. */

bytell	= SIZ1 & SIZ0 & A0
	# !SIZ1 & !SIZ0
	# A1 & A0
	# SIZ1 & A1 ;

bytelh	= A1 & !A0
	# !SIZ1 & !SIZ0 & !A1
	# !A1 & SIZ0 & SIZ1
	# A0 & !A1 & !SIZ0 ;
		   
bytehl	= !SIZ0 & !A1
	# !A1 & A0
	# SIZ1 & !A1 ;

bytehh	= !A1 & !A0 ;

/**  Logic Equations  **/

/* Here are the actual CAS terms.  Each CAS output contains a DMA term,
   activated by the appropriate 68000 bus data strobe, a normal term,
   activated by the appropriate 68020 byte select equation, and the
   a refresh term, which is activated only by the REFCAS signal. */

CAS0LL	=  BGACK & lowen &     A1 & LDS
	# !BGACK & lowen & bytell &  DS
	# REFCAS ;

CAS1LL	=  BGACK & highen &     A1 & LDS
	# !BGACK & highen & bytell &  DS
	# REFCAS ;

CAS0LH	=  BGACK & lowen &     A1 & UDS
	# !BGACK & lowen & bytelh &  DS
	# REFCAS ;

CAS1LH	=  BGACK & highen &     A1 & UDS
	# !BGACK & highen & bytelh &  DS
	# REFCAS ;

CAS0HL	=  BGACK & lowen &    !A1 & LDS
	# !BGACK & lowen & bytehl &  DS
	# REFCAS ;

CAS1HL	=  BGACK & highen &    !A1 & LDS
	# !BGACK & highen & bytehl &  DS
	# REFCAS ;

CAS0HH	=  BGACK & lowen &    !A1 & UDS
	# !BGACK & lowen & bytehh &  DS
	# REFCAS ;

CAS1HH	=  BGACK & highen &    !A1 & UDS
	# !BGACK & highen & bytehh &  DS
	# REFCAS ;