PARTNO	  390293-01 ;
		NAME	  U501 ;
		DATE	  July 27, 1988 ;
		REV	  16 ;
		DESIGNER  Welland/Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  312828 ;
		LOCATION  U501 ;

/******************************************************************/
/*								  */
/*  68020 MMU	UDS and LDS generation. Amiga AS generation,	  */
/*		Amiga RW generation, DRAM WRITE generation, and   */
/*		Amiga DTACK generation. 			  */
/*								  */
/******************************************************************/
/*  Allowable Target Device Types: 20L8A (390325-01)		  */
/******************************************************************/
/*  Free Pins: 23(I)						  */
/******************************************************************/
/*  HISTORY							  */
/*	DBH Nov  1:	Qualified /AAS for offboard accesses	  */
/*	DBH Feb 22:	Qualified other motherboard signals	  */
/*	DBH Jul 27:	BOSS qualifies signals for 68KMODE switch */
/******************************************************************/

/**  Inputs  **/

PIN 1	     = !CYCEND	 ;	/* Cycle end */
PIN 2	     = !DSEN	 ;	/* Data strobe enable */
PIN 3	     = !BOSS	 ;	/* We are the boss of the buss */
PIN 4	     = A0	 ;	/* Adress line 0 */
PIN [5..6]   = [SIZ0..1] ;	/* Data size bits */
PIN 7	     = !TRISTATE ;	/* Bus tristate control */
PIN 8	     = PRW	 ;	/* processor read write */
PIN 9	     = !ONBOARD  ;	/* Access was to onboard device */
PIN 10	     = !MEMSEL	 ;	/* Memory selected */
PIN 11	     = !DMADSACK ;	/* DTACK enable signal */
PIN 13	     = !ABGACK	 ;	/* Amiga buss request */
PIN 14	     = !ASEN	 ;	/* Adress strobe enable delayed */

/**  Outputs  **/

PIN 15	     = TS	 ;	/* Active high tristate */
PIN 16	     = !LDS	 ;	/* Lower data strobe */
PIN 17	     = !AAS	 ;	/* Amiga adress strobe */
PIN 18	     = ARW	 ;	/* Amiga RW */
PIN 19	     = !UDS	 ;	/* Active high TRISTATE signal */
PIN 20	     = !BGACK	 ;	/* Buss grant signal */
PIN 21	     = DTACK	 ;	/* Upper data strobe */
PIN 22	     = !OVR	 ;	/* Override */

/** Declarations and Intermediate Variable Definitions **/

ds	 =	((DSEN & !CYCEND & !PRW) # (ASEN & !CYCEND & PRW));
as	 =	(ASEN & !CYCEND);
offboard =	!(ONBOARD # MEMSEL);

/**  Logic Equations  **/

/* 68000 style data strobes.  These are kept in tri-state when the 
   TRISTATE signal is active, or when we're not "offboard". */

UDS	 = ds & !A0 ;
LDS	 = (ds & SIZ1)
	 # (ds & !SIZ0)
	 # (ds & A0) ;

/* 68000 style address strobe. Again, this only becomes active when the
   TRISTATE signal is negated and the memory cycle is for an offboard
   resource.
 */
AAS	 = as ;

/* This signal is the Amiga bus RW line. This signal tristates when we are 
   not yet boss and when there is a DMA device active, or during an
   onboard cycle. 
*/
ARW	 = PRW ;

/*	DTACK and OVR
 *
 *	These signals are active when a DMA device gets onto the bus
 *	and tries to access the onboard RAM. We must assert OVR so that
 *	we can control DTACK directly. This is neccessary so that we
 *	can insert wait states for refresh. DTACK is asserted after
 *	any refresh is needed and some fixed delay after AS. This fixed
 *	delay also allows OVR to take affect in tri-stating the GARY
 *	DTACK output.
 */

DTACK	 = BGACK & MEMSEL & DMADSACK & AAS;

OVR	 = BGACK & MEMSEL & AAS;
OVR.OE	 = BGACK & MEMSEL & AAS;

/*	This signal is needed for the buffers that we want enabled when
 *	WE own the buss.
 */
TS	 = TRISTATE;

/*	We keep ABGACK disconnected from BGACK until we are BOSS.
 */
BGACK	 = ABGACK;
BGACK.OE = BOSS;

[UDS, LDS, ARW, AAS].OE = !TRISTATE & offboard & BOSS;