PARTNO	  390285-01 ;
		NAME	  U308;
		DATE	  July 27, 1988;
		REV	  5 ;
		DESIGNER  Welland/Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  312828 ;
		LOCATION  U308;

/******************************************************************/
/*								  */
/*  68020 MMU	BOSS generation, E (and refresh) counter, E clock */
/*		synchroniser.					  */
/*								  */
/******************************************************************/
/*  Allowable Target Device Types: 16R6A (390115-01)		  */
/******************************************************************/
/*  Free Pins: NONE						  */
/******************************************************************/
/*  HISTORY							  */
/*	DBH Dec 23:	Moved REGRESET for JMODE logic to work	  */
/*	DBH Dec 23:	Added 68KMODE logic			  */
/*	DBH Dec 23:	Changed reset logic for FULLRESET	  */
/*	DBH Dec 23:	Replaced ABR input with JMODE input	  */
/*	DBH Dec 23:	Changed B2000 logic level for R4.0 spec   */
/*	DBH Dec 23:	Renamed GRESET->REGRESET for R4.0 spec	  */
/******************************************************************/

/**  Inputs  **/

PIN 2	     = E	 ;	/* The 6800 E clock */
PIN 3	     = B2000	 ;	/* We are in a B2000 machine */
PIN 4	     = !DTACK	 ;	/* 68000 DTACK signal */
PIN 5	     = JMODE	 ;	/* Special Johann reset mode */
PIN 6	     = !ABG	 ;	/* Amiga bus grant */
PIN 7	     = !AAS	 ;	/* Amiga address strobe */
PIN 8	     = !FULLRESET;	/* System reset */
PIN 9	     = MODE68K	 ;	/* Force us back to the 68000 */
PIN 19	     = !RESET	 ;	/* Plain old system reset */

/**  Outputs  **/

PIN 12	     = !BOSS	 ;	/* We are the BOSS of the bus */
PIN [13..16] =	[A0..3]  ;	/* counter bits 0..3 */
PIN 18	     = !REGRESET ;	/* Global reset */

/**  Used Internally **/

PIN 17	     = ESYNC	 ;	/* the E clock synchroniser */

/** Declarations and Intermediate Variable Definitions **/

sync = !ESYNC # E;

/**  Logic Equations  **/

/* BOSS is the signal used by the B2000 to take over from the 68000 on 
   the main board (by becoming a primary bus master). Our board uses
   BOSS to indicate that we have control of the bus.  The inverse of 
   BOSS is used as a CPU, MMU and Rom control register reset. BOSS gets 
   asserted after we request the bus from the 68000 (we wait until it 
   starts it's first memory access after reset) and recieve bus grant 
   and the indication that the 68000 has completed the current cycle. 
   BOSS gets held true in a latching term until the next FULLRESET or 
   until 68KMODE is asserted and we're not in a cycle.  BOSS looks like
   RESET to the 68020, BGACK to the 68000.  */

BOSS	= ABG & !AAS & !DTACK & !FULLRESET & B2000 & !MODE68K
	# BOSS & !FULLRESET & !MODE68K
	# BOSS & DTACK
	# BOSS & AAS
	# !B2000 & !FULLRESET ;

/* REGRESET is the ROM configuration register reset line.  No 
   special reason for it to be synchronous.  */

REGRESET.D = !JMODE & FULLRESET
 	   #  JMODE & RESET ;

/* ESYNC is simply a one clock delay of E. It is used by the counter
   to do edge detection. When a high to low transition of the E	clock 
   is detected, the counter is forced to a known state. This allows an 
   absolute count to be used for VMA and peripheral DTACK.  This sync-up
   is only required when the board is in a B2000, since that board will 
   be receiving E from the motherboard.  On an A2000, the E clock is 
   absent (because the processor is pulled) and thus WE create the E 
   clock, and can create it in such a way as to make it automatically 
   synced. */

ESYNC.D  = E & B2000;

/* The counter bits A0 .. A3 are used by both the 6800 cycle logic and 
   the DRAM refresh logic.  The 6800 cycle logic uses the counter to 
   generate the E clock and VMA and to sync DTACK to the E clock.  The 
   DRAM refresh logic uses the counter as the first phase in a larger 
   counter. */

!A0.D	=  A0 & sync ;

!A1.D	= !A1 & !A0
	#  A1 &  A0
	#  A3 
	# !sync ;

!A2.D	= !A2 & !A0
	# !A2 & !A1
	#  A2 &  A1 & A0
	# !sync ;

!A3.D	= !A3 & !A2 & sync
	# !A1 &  A0 & sync
	# !A3 & !A0 & sync ;