PARTNO	  390292-01 ;
		NAME	  U307 ;
		DATE	  Apr 5, 1988 ;
		REV	  14 ;
		DESIGNER  Welland/Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  312828 ;
		LOCATION  U307 ;

/******************************************************************/
/*								  */
/*  68020 MMU	Address and Data control, MMU buffer control, 	  */
/*		68020/MMU DMA arbitration.			  */
/*								  */
/******************************************************************/
/*  Allowable Target Device Types: 20L8A (390325-01)		  */
/******************************************************************/
/*  Free Pins: NONE						  */
/******************************************************************/
/*  HISTORY							  */
/*	DBH Dec 22:	Removed unused inputs			  */
/*	DBH Apr  5:	Added safe LBGACK arbitration		  */
/*	DBH Apr  5:	Added LBGACK on BG to remove BG bounce	  */
/******************************************************************/

/**  Inputs  **/

PIN 1	     = !BOSS	 ;	/* Indicates that we are boss */
PIN 2	     = !BGACK	 ;	/* '020 Bus grant acknowledge */
PIN 3	     =	PRW	 ;	/* '020 RW line */
PIN 4	     =	A1	 ;	/* Address line A1 */
PIN 5	     = !BG	 ;	/* Physical bus grant */
PIN 6	     = !DSACK1	 ;	/* Data strobe acknowledge #1 */
PIN 7	     = !VBGACK	 ;	/* Virtual address bus bus grant ack */
PIN 8	     = !VAS	 ;	/* Virtual address bus address strobe */
PIN 9	     = !AS	 ;	/* Address strobe */
PIN 10	     = !ONBOARD  ;	/* This is an onboard access */
PIN 11	     = !AAS	 ;	/* Amiga Address strobe */
PIN 13	     = !MEMSEL	 ;	/* onboard memory is being accessed */
PIN 14	     = !LBRO	 ;	/* Logical bus request out */
PIN 23	     = !LBRI	 ;	/* Logical bus request in */

/**  Outputs  **/

PIN 15	     = !ADDIR	 ;	/* Amiga data direction control */
PIN 16	     = !ADOEH	 ;	/* Amiga data output enable high word */
PIN 17	     = !ADOEL	 ;	/* Amiga data output enable low word */
PIN 18	     = !LBGACK	 ;	/* Virtual Bus grant acknowledge out */
PIN 19	     =	DRSEL	 ;	/* Data register select */
PIN 20	     = !MMUALL	 ;	/* MMU address latch latch control */
PIN 21	     =	MMUALOE  ;	/* MMU address latch output enable */
PIN 22	     = !LBR	 ;	/* Logical bus request (68020 BR) */

/** Declarations and Intermediate Variable Definitions **/

/**  Logic Equations  **/

/* The main thing with data direction is who's the boss and whether 
   they're reading or writing.  Much like D2P in BUSTER, only simpler */

ADDIR	 = (BGACK & !PRW)
	 # (!BGACK & PRW);

/* Two buffers to enable, high and low data buffers.  If we're not the
   BOSS, they stay in tri-state.  If we are, they only get enabled on
   the appropriate transactions with the motherboard.  The high order
   data bus is also the 16 bit data bus under '020 control, so we use
   that for all non-DMA activity involving the motherboard.  For DMA,
   we can only talk to memory.  Based on which word the DMA device is
   interested in, we enable either the high or the low data bus.
*/

ADOEH	 = (BOSS & BGACK &  MEMSEL & !A1 & AAS)
	 # (BOSS & !BGACK & !ONBOARD & !MEMSEL & AS);
ADOEL	 = (BOSS & BGACK & MEMSEL & A1 & AAS);

/* This selects the latching mode of the '646 buffers.  The only time
   we want to latch data is when the 68020 reads from the A2000. */

DRSEL	 = BOSS & PRW & !BGACK;

/* Here are the MMU controls.  */

MMUALL	 = !VBGACK & !VAS;
MMUALOE  = BGACK;

/* This is the logical bus to 68020 arbitration logic.  We request the
   bus if either an external device (via LBRI = BR), wants it, or the 
   MMU itself (via LBRO) wants the bus.  Once LBGACK is asserted, this
   should go away, at least if we're an external device. */

LBR	 = LBRO 
	 # LBRI & !LBGACK;

/* Now for acknowledging the bus.  We want to acknowledge the 68020's bus
   grant based on external requests (via BGACK) or MMU driven requests
   (via VBGACK).  The A2000 system can't be certain that there's no
   activity on the logical bus (or the 32 bit bus, for that matter), so
   we check VAS and DSACK0 here for it.  The MMU does this checking 
   anyway, but I duplicated it here just for consistency.  I'm also
   being polite enough to check if there's already a VBGACK from the
   MMU before asserting my physical bus driven BGACK.

   One problem creeps into this logic.  It seems that on most A2000 DMA
   requests, LBGACK was coming out so late that the 68020 started to 
   retry VBG.  I didn't like this, so I use BG (the physical bus grant)
   to start LBGACK, since I can check for cycle end right here.  
*/
   
LBGACK	= VBGACK & !DSACK1 & !VAS
	# LBGACK &  VBGACK
	#  BGACK & !DSACK1 & !VAS & !VBGACK
	# LBGACK &  BGACK 
	#  BG	 & !DSACK1 & !VAS & !VBGACK 
	# LBGACK &  BG & !BGACK & !VBGACK ;