PARTNO	  390291-01 ;
		NAME	  U306;
		DATE	  July 27, 1988 ;
		REV	  12 ;
		DESIGNER  Welland/Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  312828 ;
		LOCATION  U306;

/******************************************************************/
/*								  */
/*  A2620	FPU chip select, Avec generation, Bus request	  */
/*		arbitration, amiga bus grant and refresh bus	  */
/*		grant generation.				  */
/*								  */
/******************************************************************/
/*  Allowable Target Device Types: 20L8B (390326-01)		  */
/******************************************************************/
/*  Free Pins: NONE						  */
/******************************************************************/
/*  HISTORY							  */
/*	DBH Dec 22:	Renamed MMURESET->GRESET as per R4.0      */
/*	DBH Dec 22:	B2000 input is unused, removed it.	  */
/*	DBH Feb 17:	Reworked for understanding, no changes.	  */
/*	DBH Jul 27:	Changed BG to BGSYNC for Rev 3.0 board.	  */
/******************************************************************/

/**  Inputs  **/

PIN [1..3]   = [FC2..0]  ;	/* Function control lines from the '020 */
PIN 4	     = !BGACK	 ;	/* Buss Grant Acknowledge */
PIN 5	     = !BOSS	 ;	/* We are boss */
PIN 6	     = !SENSE	 ;	/* SENSE line from the 68881 */
PIN 7	     = !ABR	 ;	/* Amiga bus request */
PIN [8..11]  = [VA19..16];	/* Virtual address lines VA19-16 */
PIN [13,14]  = [VA15,VA14];	/* Virtual address lines VA15-14 */
PIN 23	     = VA13	 ;	/* Virtual address VA23 */
PIN 19	     = !BGSYNC	 ;	/* Bus grant synced to 7M clock */

/**  Outputs  **/

PIN 15	     = !FPUCS	 ;	/* Floating point unit chip select */
PIN 16	     = !AVEC	 ;	/* Avec generation for a interrupt cycle */
PIN 17	     = !GRESET   ;	/* Global reset signal */
PIN 18	     = !BR	 ;	/* Bus request */
PIN 22	     = !BERR	 ;	/* Buss error iff !SENSE & FPUCS */
PIN 20	     = !ABG	 ;	/* Amiga bus grant */

/** Declarations and Intermediate Variable Definitions **/

field cpustate	= [FC2..0] ;			/* CPU state types */
cpuspace	= (cpustate:7) ;
userspace	= (cpustate:1 # cpustate:2) ;
superspace	= (cpustate:5 # cpustate:6) ;

field spacetype	= [VA19..16] ;			/* CPU space type */
interruptack	= (spacetype:f0000) ;
coppercom	= (spacetype:20000) ;
breakpoint	= (spacetype:00000) ;

field copperid	= [VA15..13] ;			/* Copper types */
mc68881		= (copperid:2000) ;

/**  Logic Equations  **/

/* This selects the 68881 or 68882 math chip, as long as there's no
   DMA going on.  If the chip isn't there, we want a buss error
   generated to force an F-line emulation exception. */

FPUCS	 = cpuspace & coppercom & mc68881 & !BGACK;

BERR	 = cpuspace & coppercom & mc68881 & !SENSE & !BGACK;
BERR.OE  = cpuspace & coppercom & mc68881 & !SENSE & !BGACK;

/* This forces all interrupts to be serviced by autovectoring.  None
   of the built-in devices supply their own vectors, and the system is
   generally incompatible with supplied vectors, so this shouldn't be
   a problem working all the time.  During DMA we don't want any AVEC
   generation, in case the DMA device is like a Boyer HD and doesn't
   drive the function codes properly.  */

AVEC	 = cpuspace & interruptack & !BGACK;

/* We must make sure that the first bus request wins the bus
   and is not interrupted by a later bus request. */

BR	 = ABR & BOSS;

/* If ABG is asserted too close to the arbitration clock in BUSTER,
   we can lose a race, and the bus arbiter will lock up.  Bad news
   in anyone's book.  So BG is externally synced with the 7M
   clock to make BGSYNC.  Since the 68000 bases it's BG on the
   rise of 7M too, we should be in good shape.  All the PAL has to
   do is tri-state this when we're not the BOSS.  Sounds easy...
*/

ABG	 = BGSYNC & BOSS ;
ABG.OE	 = BOSS;

/* System-wide reset signal */

GRESET = !BOSS;