PARTNO	  390290-01 ;
		NAME	  U305 ;
 		DATE	  July 12, 1988 ;
		REV	  8 ;
		DESIGNER  Welland/Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  312828 ;
		LOCATION  U305 ;

/******************************************************************/
/*								  */
/*  68020 MMU	RAM address decode, Tristate generation and ABR   */
/*		generation.					  */
/*								  */
/******************************************************************/
/*  Allowable Target Device Types: 20L8B (390326-01)		  */
/******************************************************************/
/*  Free Pins: NONE
/******************************************************************/
/*  HISTORY							  */
/*	DBH Dec 22:	Modified comparator for 2Meg/4Meg	  */
/*	DBH Dec 22:	Added A2000->68020 Buss Error Logic	  */
/*	DBH Dec 22:	Added MODE68K to ABR function		  */
/*	DBH Dec 22:	Moved pins as per R4.0 spec		  */
/*	DBH Feb 23:	Fixed comparator for real 4Meg operation  */
/*	DBH Feb 23:	Added BANK output for DRAM control	  */
/*	DBH Feb 23:	Changed MEMSEL to make it faster	  */
/*	DBH Jul 12:	Added A24 for special addressing feature  */
/******************************************************************/

/*
	MEMSEL is an output indicating that the address bus matches the
	address bits in the configuration register if the register is
	configured.

	TRISTATE is an output used to tristate all signals that go
	to the amiga bus. This is done on powerup before BOSS is
	asserted and whenever an Amiga DMA device has control of
	the Amiga Bus.

	ABR is the Amiga bus request output. This signal is only
	asserted by this PAL on powerup in order to get the bus
	so that we can assert BOSS, and it won't be asserted if 
	MODE68K is asserted.

	RAMSIZ is now used to indicate 2Meg vs. 4Meg to the Autoconfigure
	"ROM" implemented in this PAL.  RAMSIZ asserted indicates 4Meg,
	RAMSIZ negated indicates 2Meg.

	The A24 bit allows addressing above the 24 bit 68000 limit,
	however, due to OR-term limitations, a special version of this
	PAL will be required to take advantage of this.
*/

/**  Inputs  **/

PIN [1..3]   = [RA2..0];	/* Register address bits 23-21 */
PIN 4	     = !BEER	 ;	/* Amiga2000's Bus Error Signal */
PIN 5	     = CONFIGED  ;	/* RAM configuration register is valid */
PIN 6	     = !RAMSIZ	 ;	/* RAM size, 2Megs or 4Megs */
PIN [7..9]   = [A2..0] ;	/* Address bits A23-21 */
PIN 10	     = !BGACK	 ;	/* Buss grant acknowledge from the '020 */
PIN 11	     = !BOSS	 ;	/* We are the boss of the bus */
PIN 13	     = !RESET	 ;	/* The system reset line */
PIN 14	     = !AAS	 ;	/* The amiga address strobe */
PIN 20	     = MODE68K	 ;	/* Make the 68000 the boss, fatally */
PIN 23	     = !AS	 ;	/* The '851 address strobe */
PIN 17	     = A24	 ;	/* Address bit 24 */

/**  Outputs  **/

PIN 15	     = !MEMSEL	 ;	/* Memory select output */
PIN 16	     = !BERR	 ;	/* System Buss Error Signal */
PIN 21	     = ABR	 ;	/* Amiga bus request output */
PIN 22	     = !TRISTATE ;	/* Tristate all amiga bus lines */
PIN 18	     = !BANK	 ;	/* Which DRAM bank to access? */
PIN 19	     = !DMAMEM	 ;	/* Memory select for DMA */

/** Declarations and Intermediate Variable Definitions **/

/* There are a possible 8 slots for any 2 meg board in the 16 meg address
   space.  Only 4 of these slots can actually be used.  */

field slot	= [RA2..0] ;	/* Autoconfiged base address */
field cpu	= [A2..0] ;	/* Actual bus address */

/* This equation indicates a valid memory access for the on-board RAM, either
   2 meg or 4 meg versions.  Either board can talk to the 2 meg slot that
   starts at the autoconfigured base address, and this is always on an
   even 2 meg boundary.  A 4 meg board can also talk to the next 2 meg slot.
   However, there is no "next" 2 meg slot after slot4, so a 4 meg board can
   never exist in slot 4. */

access	= (slot:1 & cpu:1)		/* Either case here */
	# (slot:1 & cpu:2 & RAMSIZ)	/* 4 Meg only */
	# (slot:2 & cpu:2)		/* Either case here */
	# (slot:2 & cpu:3 & RAMSIZ)	/* 4 Meg only */
	# (slot:3 & cpu:3)		/* Either case here */
	# (slot:3 & cpu:4 & RAMSIZ)	/* 4 Meg only */
	# (slot:4 & cpu:4 & !RAMSIZ);	/* 2 Meg only */

/**  Logic Equations  **/

/* The DRAM Bank selected is based on slot matching.  We normally want
   the first bank, and we get that for all 2 meg accesses, and for
   4 meg accesses in the base slot.  For 4 meg access of the next
   slot, we go to the second bank.  If we're not configed, the extra
   memory is up high, and we're in the second bank on odd slot
   boundaries. */

BANK	= slot:1 & cpu:2 & RAMSIZ & CONFIGED
	# slot:2 & cpu:3 & RAMSIZ & CONFIGED
	# slot:3 & cpu:4 & RAMSIZ & CONFIGED;

/* This is the actual comparison test.  Added in here are the additional
   qualifiers that indicate the board must be configured, and the proper
   address strobe action based on the DMA state.  Also, consider the case
   of being outside the normal RAM space.  Here we'll take either of
   the first two slots. */

MEMSEL	  = access & CONFIGED & AS ;

MEMSEL.OE = !BGACK ;

DMAMEM	  = access & CONFIGED & AAS ;
DMAMEM.OE = BGACK ;

/* We want tristate when we're not BOSS, or when we are BOSS but we're 
   being DMAed. */

TRISTATE = !BOSS # (BOSS & BGACK);

/* When we're first up after a global reset, we want to request the bus
   from the 68000.  However, if we're in 68K mode, we don't want to
   request the bus. */

ABR	 = (!RESET & AAS & !BOSS & !MODE68K) #
	   (!RESET & ABR & !BOSS & !MODE68K);

/* Bus error from the A2000 should be seen by the 68020, but not the
   other way around, or autoconfig devices will get messed up. */

BERR	 = BEER ;
BERR.OE	 = BEER ;