PARTNO	  390288-01 ;
		NAME	  U301;
		DATE	  July 6, 1988 ;
		REV	  8 ;
		DESIGNER  Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  312828 ;
		LOCATION  U301;

/******************************************************************/
/*								  */
/*  68020 MMU	Autoconfig control and reset generation 	  */
/*								  */
/******************************************************************/
/*  Allowable Target Device Types: 20L8A (390325-01)		  */
/******************************************************************/
/*  Free Pins: NONE						  */
/******************************************************************/
/*  HISTORY							  */
/*	DBH Dec 22:	Adjusted autoconfig for 2Meg/4Meg option. */
/*	DBH Jul  6:	WARNING! REQUIRES G4 or later ROM.	  */
/*	DBH Jul  6:	Changed registers for autoconfig.	  */
/*	DBH Jul  6:	Added OSMODE input. 			  */
/******************************************************************/

/**  Inputs  **/

PIN 1	     = !CSAUTO	 ;	/* Autoconfig chip select */
PIN 2	     = !RAMSIZ	 ;	/* Indicates the amount of RAM onboard */
PIN 3	     = !DS	 ;	/* Data Strobe */
PIN 4	     =	PRW	 ;	/* Processor read write */
PIN 5	     = !BOSS	 ;	/* Indicates that we are the boss ! */
PIN 6	     = !CPURESET ;	/* The cpu reset line */
PIN 9	     =	A1	 ;	/* Address line 1 */
PIN 10	     =	A2	 ;	/* Address line 2 */
PIN 11	     =	A3	 ;	/* Address line 3 */
PIN 13	     =	A4	 ;	/* Address line 4 */
PIN 14	     =	A5	 ;	/* Address line 5 */
PIN 23	     =	A6	 ;	/* Address line 6 */
PIN 7	     =	CONFIGED ;	/* Indicates the board is autoconfiged */
PIN 8	     =	RESENB	 ;	/* Enable for 68020 reset feedback */
PIN 21	     =	OSMODE	 ;	/* Operating system preference */

/**  Outputs  **/

PIN 15	     = !D31	 ;	/* Data line 31 */
PIN 16	     = !D30	 ;	/* Data line 30 */
PIN 17	     = !D29	 ;	/* Data line 29 */
PIN 18	     = !D28	 ;	/* Data line 28 */
PIN 19	     = !ROMCLK	 ;	/* Rom control register clock */
PIN 20	     = !RAMCLK	 ;	/* RAM control register clock */
PIN 22	     =	RESET	 ;	/* System Reset */

/** Declarations and Intermediate Variable Definitions **/

field addr = [A6..1];

romaddr    = (addr:40);
ramaddr    = (addr:48);

writecycle = (CSAUTO & !PRW & DS & !CPURESET);
readcycle  = (CSAUTO & PRW & DS & !CPURESET);

/**  Logic Equations  **/
/*
	The RESET output feeds to the /RST signal from the A2000
	motherboard.  Which in turn enables the assertion of the /BOSS
	line when you're on a B2000.  Which in turn creates the
	/CPURESET line.  Together these make the RESET output.	In
	order to eliminate the glitch on RESET that this loop makes,
	the RESENB input is gated into the creation of RESET.  What
	this implies is that the 68020 can't reset the system until
	we're RESENB, OK?.  Make sure to consider the effects of this
	gated reset on any special use of the ROM configuration register.
	Using JMODE it's possible to reset the ROM configuration register
	under CPU control, but not if the RESENB line is negated.

	RAMSIZ is now used to indicate 2Meg vs. 4Meg to the Autoconfigure
	"ROM" implemented in this PAL.  RAMSIZ asserted indicates 4Meg,
	RAMSIZ negated indicates 2Meg.
 */

D31	 = addr:02
	 # addr:0c & !OSMODE & !CONFIGED;
D30	 = addr:04
	 # addr:08 & CONFIGED;
D29	 = addr:12 & CONFIGED
	 # addr:16 & CONFIGED;
D28	 = addr:00
	 # addr:02 & !RAMSIZ
	 # addr:04 ;

ROMCLK	 = (writecycle & romaddr & !CONFIGED) #
	   (ROMCLK & DS);

RAMCLK	 = (writecycle & ramaddr & !ROMCLK) #
	   (!CPURESET & RAMCLK);

RESET	 = BOSS & CPURESET & RESENB;

[D31..28].OE =	readcycle & !RAMCLK;