PARTNO		U681 ;
		NAME		U681 ;
		DATE		October 28, 1992 ;
		REV		0 ;
		DESIGNER	Haynie ;
		COMPANY		Commodore ;
		ASSEMBLY	Nyx ;
		LOCATION	West Chester ;
		DEVICE		g22v10 ;

/************************************************************************/
/*									*/
/*	Nyx	Interrupt latch, primary bus arbitration		*/
/*									*/
/*	This device manages interrupt debouncing, to eliminate any	*/
/*	phantom level 7 interrupts.  It also asserts a level 7 		*/
/*	interrupt in response to a SAD triggering event, and it 	*/
/*	manages the local bus arbitration.				*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-15	 			*/
/************************************************************************/
/*  Clock:		7Mhz						*/
/************************************************************************/
/*  Free Pins:		21(IO),22(IO)					*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Oct 28:	Decended from A3000+ U681, Rev 2		*/
/************************************************************************/

/** INPUTS: **/

PIN 1		=  CLK		;	/* Interrupt latch clock */
PIN 2		=  C7M		;	/* 7MHz clock */
PIN 3		= !CIPL0	;	/* Chip conditioned interrupts */
PIN 4		= !CIPL1	;
PIN 5		= !CIPL2	;
PIN 6		= !BOSS		;	/* Processor card is active */
PIN 7		= !CBR		;	/* Processor card bus request */
PIN 8		= !BR		;	/* Buster's bus request */
PIN 9		= !INTEN	;	/* Interrupt enable */
PIN 10		= !SADTRIG	;	/* SAD interrupt trigger */
PIN 11		= !CDAC		;	/* 90 degree 7MHz clock */
PIN 13		= !SADRT	;	/* SAD remote trigger */
PIN 19		= !SADEN	;	/* SAD interrupt trigger enable */

/** OUTPUTS: **/

PIN 14		= !BG		;	/* Bus grant out to Buster */
PIN 15		= !BG30		;	/* Emulated '030 bus grant. */
PIN 16		= !IPL2		;
PIN 17		= !IPL1		;
PIN 18		= !IPL0		;	/* CPU interrupts */
PIN 23		=  CLKOUT	;	/* Interrupt latch clock */

/** USED INTERNALLY: */

PIN 20		= !SADBOUNCE	;	/* Debouncing for SAD triggers. */

/**  OUTPUT TERMS:  **/

/* This is the interrupt latch clock.  */

CLKOUT		= CDAC;

/* Here we drive the interrupt bits. Ordinarily, I try to filter out any
   level 7 interrupt glitches, but when a SAD trigger event takes place,
   I have to go with it. */

IPL2.D		= INTEN & CIPL2 & !CIPL1
		# INTEN & CIPL2 & !CIPL0
		# SADEN & SADBOUNCE & SADTRIG
		# SADEN & SADBOUNCE & SADRT;

IPL1.D		= INTEN & CIPL1
		# SADEN & SADBOUNCE & SADTRIG
		# SADEN & SADBOUNCE & SADRT;

IPL0.D		= INTEN & CIPL0
		# SADEN & SADBOUNCE & SADTRIG
		# SADEN & SADBOUNCE & SADRT;
	
/* The SAD debugger generates a level 7 interrupt via one of two triggers.
   This line debounces that tigger pulse somewhat. */

SADBOUNCE.D	= SADEN & SADTRIG
		# SADEN & SADRT;

/* When CBR is asserted, I drive BG30 right back to simulate a 68030 bus
   arbitration.  */


BG30		= CBR
		# BG30 & !BOSS;

/* The system bus version of BG* is never driven here.  The CPU card will
   drive it directly once it acquires the bus. */

BG		= 'b'1;
BG.OE		= !BOSS;