PARTNO		U282 ;
		NAME            U282 ;
		DATE            September 1, 1993 ;
		REV             1 ;
		DESIGNER        Dave Haynie ;
		COMPANY         Commodore ;
		ASSEMBLY        Nyx ;
		LOCATION        West Chester ;
		DEVICE		g22v10 ;

/************************************************************************/
/*									*/
/*  	Nyx	Chip RAM Module Mapper, Part 1				*/
/*									*/
/*	This is one of two devices used to help map module ID codes 	*/
/*	into proper AAA autoconfig codes.  				*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-25				*/
/************************************************************************/
/*  Clock:		NONE						*/
/************************************************************************/
/*  Free Pins:		21(IO)						*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Oct 15:	Completely new.					*/
/*	DBH Sep  1:	Disable ID buffer altogether if no module is 	*/
/*			asserting.					*/
/************************************************************************/

/** INPUTS: **/

PIN [1..10]	= [MC9..0]	;	/* Module config codes. */
PIN 11		= !CFGRD	;	/* Chip-RAM configuration strobe */
PIN 13		=  DUAL_SING	;	/* The Chip-RAM bus size */

/** OUTPUTS: **/

PIN 14		= !BUFEN	;	/* Turn on the configuration buffer */
PIN 15		=  FIL2		;	/* Slot 2 is filled. */
PIN 16		=  FIL3		;	/* Slot 3 is filled. */
PIN 17		=  BLT32	;	/* External blitter in slots 3 & 2. */
PIN 18		=  VRM32	;	/* VRAM is in slots 3 & 2. */
PIN 19		=  FIL4		;	/* Slot 4 is filled. */
PIN 20		=  FIL5		;	/* Slot 5 is filled. */
PIN 22		=  FIL76	;	/* Slots 7 & 6 are filled. */
PIN 23		=  RAMSIZE	;	/* RAM size for all banks. */

/** INTERMEDIATE TERMS: **/

/* The module code lines are in MC9..MC0.  There are five bits for each
   module, with the following definitions:


	bit	meaning

	 0	1 = VRAM. 0 = DRAM
	 1	1 = Satellite blitter, 0 = plain memory
	 2	\ 0 = 4MB, 1 = 2MB, 2 = 1MB, 3 = Empty
	 3	/
	 4	1 = 32-bit, 0 = 64-bit


   The module should be ignored is we have any 32-bit module in a 64-bit
   system. */


/* The VRAM, BLIT, and size encodings are very straight forward. */

m0isVRAM	=  MC0;

m0hasBLIT	=  MC1;

m0is64		= !MC4;

m1isVRAM	=  MC5;

m1hasBLIT	=  MC6;

m1is64		= !MC9;

/* If there's a sizing conflict, for now we disable all of the memory.
   This should be pretty obvious to the user.  This is the disable
   signal. */

modsOK		= !m0is64 & DUAL_SING
		# !m1is64 & DUAL_SING;

/* The variables below decode the simple conditions for each slot, to make the
   output terms read easier. */

m0isEmpty	=  MC3 &  MC2
		# !modsOK;

m0is1MB		=  MC3 & !MC2 & modsOK;

m0is2MB		= !MC3 &  MC2 & modsOK;

m0is4MB		= !MC3 & !MC2 & modsOK;


m1isEmpty	=  MC8 &  MC7
		# !modsOK;

m1is1MB		=  MC8 & !MC7 & modsOK;

m1is2MB		= !MC8 &  MC7 & modsOK;

m1is4MB		= !MC8 & !MC7 & modsOK;


/** OUTPUT TERMS: **/

/* The configuration buffers for slots 3-7 turn on when CFGRD is 
   asserted. */

BUFEN		= CFGRD & !m0isEmpty
		# CFGRD & !m1isEmpty;

/* The configuration slots are based on the modules inserted and the 
   size of the bus.  A 32-bit system can use a 64-bit module, only half 
   of it is addressed.  A 64-bit system will ignore a 32-bit module.
   The filling of slots looks like this:

	MOD1	MOD0	S0  S1	S2  S3	S4  S5	S6  S7

	0M	0M	0   0	0   0	0   0	0   0
	0M	1M	1   0	0   0	0   0	0   0
	0M	2M	1   1   0   0	0   0	0   0
	0M	4M	1   1	1   1	0   0	0   0
	1M	0M	1   0	0   0	0   0	0   0
	1M	1M	1   1   0   0	0   0	0   0
	1M	2M	1   1   1   0	0   0	0   0
	1M	4M	1   1	1   1	1   0	0   0
	2M	0M	1   1   0   0	0   0	0   0
	2M	1M	1   1   1   0	0   0	0   0
	2M	2M	1   1   1   1	0   0	0   0
	2M	4M	1   1   1   1	1   1	0   0
	4M	0M	1   1   1   1	0   0	0   0
	4M	1M	1   1   1   1	1   0	0   0
	4M	2M	1   1   1   1	1   1	0   0
	4M	4M	1   1   1   1	1   1   1   1
*/


FIL76		= m0is4MB & m1is4MB;

FIL5		= FIL76
		# m0is2MB & m1is4MB
		# m0is4MB & m1is2MB;

FIL4		= FIL5
		# m0is1MB & m1is4MB
		# m0is4MB & m1is1MB;

FIL3		= FIL4
		# m0isEmpty & m1is4MB
		# m0is4MB   & m1isEmpty;

FIL2		= FIL3
		# m0is1MB & m1is2MB
		# m0is2MB & m1is1MB;


/* Both BLIT and VRAM for slots 2 and 3 have to consider if
   there's any RAM shift, so they know which module's codes
   to obey. */


BLT32		= m0hasBLIT & m0is4MB
		# m1hasBLIT & m1is2MB;

VRM32		=  m0isVRAM & m0is4MB
		#  m1isVRAM & m1is2MB;

/* RAM size says 0 = 9 line, 1 = 10 line.  Right now, I'm only supporting
   9 line DRAM, since the 10 line idea is pretty incompatible with the idea
   of modules, the way it works now.  What would be ideal is a design that
   always drives the 10th line and the proper RAS/CAS, so a 4MB module can
   choose to use four RAS* lines or the high order address line to handle
   those extra 2 bits of address space. */

RAMSIZE		= 'b'0;