PARTNO		U201 ;
		NAME            U201 ;
		DATE            October 15, 1992 ;
		REV             0 ;
		DESIGNER        Dave Haynie ;
		COMPANY         Commodore ;
		ASSEMBLY        Nyx ;
		LOCATION        West Chester ;
 		DEVICE		g22v10 ;

/************************************************************************/
/*									*/
/*  	Nyx	RAS Generator						*/
/*									*/
/*	This device generates RAS controls for each of the eight 	*/
/*	possible chip RAM banks.					*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-10				*/
/************************************************************************/
/*  Clock:		NONE						*/
/************************************************************************/
/*  Free Pins:		1(I),5(I),13(I),14(IO),23(IO)			*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Oct 15:	Completely new.					*/
/************************************************************************/

/** INPUTS: **/

PIN 2		=  DUAL_SING	;	/* System size */
PIN 3		=  RSHIFT1	;	/* RAS bank shift */
PIN 4		=  RSHIFT0	;
PIN [6..9]	= [XA0..3]	;	/* RAS bank address */
PIN 10		= !RASEN	;	/* RAS basis strobe */
PIN 11		=  RFSH		;	/* Refresh indicator */

/** OUTPUTS: **/

PIN 15		= !RAS0		;	/* Bank-specific RAS strobes. */
PIN 16		= !RAS1		;
PIN 17		= !RAS4		;
PIN 18		= !RAS5		;
PIN 19		= !RAS6		;
PIN 20		= !RAS7		;
PIN 21		= !RAS2		;
PIN 22		= !RAS3		;

/** INTERMEDIATE TERMS: **/

/* The logical banking is controlled via the XA lines and DUAL_SING.
   A quirk of the AAA system is that XA0..2 determine banking in a
   single system, XA1..3 in a dual system.  Hopefully this will be
   simplified in a future Andrea. */

bank0		= !XA2 & !XA1 & !XA0 & !DUAL_SING
		# !XA3 & !XA2 & !XA1 &  DUAL_SING;

bank1		= !XA2 & !XA1 &  XA0 & !DUAL_SING
		# !XA3 & !XA2 &  XA1 &  DUAL_SING;

bank2		= !XA2 &  XA1 & !XA0 & !DUAL_SING
		# !XA3 &  XA2 & !XA1 &  DUAL_SING;

bank3		= !XA2 &  XA1 &  XA0 & !DUAL_SING
		# !XA3 &  XA2 &  XA1 &  DUAL_SING;

bank4		=  XA2 & !XA1 & !XA0 & !DUAL_SING
		#  XA3 & !XA2 & !XA1 &  DUAL_SING;

bank5		=  XA2 & !XA1 &  XA0 & !DUAL_SING
		#  XA3 & !XA2 &  XA1 &  DUAL_SING;

bank6		=  XA2 &  XA1 & !XA0 & !DUAL_SING
		#  XA3 &  XA2 & !XA1 &  DUAL_SING;

bank7		=  XA2 &  XA1 &  XA0 & !DUAL_SING
		#  XA3 &  XA2 &  XA1 &  DUAL_SING;

refresh		= RFSH & RASEN;

noshift		= !RSHIFT1 & !RSHIFT0;

shift1		= !RSHIFT1 &  RSHIFT0;

shift2		=  RSHIFT1 & !RSHIFT0;

shift4		=  RSHIFT1 &  RSHIFT0;

/** OUTPUT TERMS: **/

/* The first RAS banks always obey the normal mapping of the XA lines. */

RAS0		= bank0 & RASEN
		# refresh;

RAS1		= bank1 & RASEN
		# refresh;

RAS2		= bank2 & RASEN
		# refresh;

RAS3		= bank3 & RASEN
		# refresh;

/* The next set of RAS banks is based as well on the RAS Shift lines.
   These lines are set by a small module placed in the first bank, in
   order to shift the bank driven to the four RAS lines in the second
   module bank. */

RAS4		= bank4 & noshift & RASEN
		# bank3 &  shift1 & RASEN
		# bank2 &  shift2 & RASEN
		# bank0 &  shift4 & RASEN
		# refresh;

RAS5		= bank5 & noshift & RASEN
		# bank4 &  shift1 & RASEN
		# bank3 &  shift2 & RASEN
		# bank1 &  shift4 & RASEN
		# refresh;

RAS6		= bank6 & noshift & RASEN
		# bank5 &  shift1 & RASEN
		# bank4 &  shift2 & RASEN
		# bank2 &  shift4 & RASEN
		# refresh;

RAS7		= bank7 & noshift & RASEN
		# bank6 &  shift1 & RASEN
		# bank5 &  shift2 & RASEN
		# bank3 &  shift4 & RASEN
		# refresh;