PARTNO		U123 ;
		NAME            U123 ;
		DATE            October 15, 1992 ;
		REV             0 ;
		DESIGNER        Dave Haynie ;
		COMPANY         Commodore ;
		ASSEMBLY        Nyx ;
		LOCATION        West Chester ;
		DEVICE		g22v10 ;

/************************************************************************/
/*									*/
/*  	Nyx	ID/Clock Generator					*/
/*									*/
/*	This PAL generates the monitor ID and sources PCLK and MCLK,	*/
/*	taking into account XCLK and XCLKEN.				*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-10				*/
/************************************************************************/
/*  Clock:		XCLK						*/
/************************************************************************/
/*  Free Pins:		7(I),8(I),17(IO),18(IO),22(IO)
/************************************************************************/
/*  HISTORY								*/
/*	DBH Oct 15:	Completely new.					*/
/************************************************************************/

/** INPUTS: **/

PIN 1		=  XCLK		;	/* External clock */
PIN 2		= !XCLKEN	;	/* External clock enable */
PIN 3		=  C57M		;	/* 57MHz clock */
PIN 4		= !MONIDEN	;	/* Monitor ID enable */
PIN 5		= !ALE		;	/* A/D bus address latch */
PIN 6		=  QCLK		;	/* Pixel clock output from switcher */
PIN 9		=  DUAL_SING	;	/* What kind of system */
PIN 10		=  MONID2	;	/* Monitor ID code */
PIN 11		=  MONID1	;
PIN 13		=  MONID0	;

/** OUTPUTS: **/

PIN [14..16]	=  [AD0..2]	;	/* A/D bus */
PIN 19		=  MCLK		;	/* AAA basis clock */
PIN 20		=  PCLK		;	/* Pixel clock */

/** USED INTERNALLY: **/

PIN 22		=  XDIV4	;	/* XCLK/4 */
PIN 23		=  XDIV2	;	/* XCLK/2 */

/** OUTPUT TERMS: **/

/* Divide downs from XCLK. */

XDIV2		= !XDIV2;

XDIV4		= !XDIV2 & !XDIV4
		#  XDIV2 &  XDIV4;

/* The Pixel clock is usually QCLK.  When XCLK takes over, it's XCLK/2
   for a single system, XCLK/4 for a double system.  There could be other
   kinds of genlocks, maybe these could key off the video slot monitor
   ID. */

PCLK		= !XCLKEN & QCLK
		#  XCLKEN & !DUAL_SING & XDIV2
		#  XCLKEN &  DUAL_SING & XDIV4;

/* The bus (memory) clock is direct for now. */

MCLK		= C57M;

/* The MONID bits gate over to the corresponding A/D bus bits based on
   the MONIDEN and ALE controls. */

AD0		= MONID0;

AD1		= MONID1;

AD2		= MONID2;

[AD2..0].OE	= MONIDEN;