PARTNO		U122 ;
		NAME            U122 ;
		DATE            April 23, 1992 ;
		REV             0 ;
		DESIGNER        Dave Haynie ;
		COMPANY         Commodore ;
		ASSEMBLY        Nyx ;
		LOCATION        West Chester ;
		DEVICE		g22v10 ;

/************************************************************************/
/*									*/
/*  	Nyx	Clock Switch PAL					*/
/*									*/
/*	This PAL is designed to switch between four asynchronous clocks	*/
/*	without slivers, in a relatively cheap-ass fashion (eg, we	*/
/*	don't have time to make Jim Redfield's "CMOS PCLK" gate array	*/
/*	and there's no room for a zillion components to do this).	*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-7 				*/
/************************************************************************/
/*  Clock:		FCLK						*/
/************************************************************************/
/*  Free Pins:		7(I),8(I),9(I),20(IO)				*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Apr 23:	Completely new.					*/
/************************************************************************/

/** Inputs **/

PIN 1		=  FCLKIN	;	/* Flip-flop clock */
PIN [2..5]	= [FREQ0..3]	;	/* The four possible clocks */
PIN 6		= !RST		;	/* System reset */
PIN 10		=  FS2		;	/* Frequency selects */
PIN 11		=  FS1		;
PIN 13		=  FS0		;

/**  Outputs  **/

PIN 23		=  FCLKOUT	;	/* Flip-flop clock output */
PIN 22		=  PCLK		;	/* Pixel clock */
PIN 21		=  SCLK		;	/* Raw clock, slivers and all */

/**  Used Internally **/

PIN 19		= !CHANGE	;	/* Ready for a change? */
PIN 18		= !CHANGING	;	/* In the changing process? */
PIN 17		= !NEWCLK	;	/* Ready for the next clock */

PIN 16		=  LS0		;	/* Latched clock selects */
PIN 15		=  LS1		;
PIN 14		=  LS2		;

/**  Declarations and Intermediate Variable Definitions  **/

/**  Logic Equations  **/

/* This is the flip-flop clock output.  Normally, we want this to
   reflect the state of the pixel clock, but we don't always know
   what the pixel clock is.

FCLKOUT		= !CHANGING & PCLK
		#  CHANGING & !NEWCLK
		#    NEWCLK & SCLK;

/* This is the pixel clock output.  The pixel clock will reflect the
   selected input clock during normal operation.  When the clock is
   changing, the pixel clock will stay high.  The change signals take
   into account the state of the input clock, so we avoid slivers. */

PCLK		= FREQ0 & !LS2 & !LS1 & !LS0
		# FREQ1 & !LS2 & !LS1 &  LS0
		# FREQ1 & !LS2 &  LS1 & !LS0
		# FREQ3 & !LS2 &  LS1 &  LS0
		# CHANGING;

/* This is the slivery clock.  It's the same as the pixel clock, but
   it isn't inhibited during clock changeover.  This basically keeps
   things moving while we're selecting the new clock. */

SCLK		= FREQ0 & !FS2 & !FS1 & !FS0
		# FREQ1 & !FS2 & !FS1 &  FS0
		# FREQ1 & !FS2 &  FS1 & !FS0
		# FREQ3 & !FS2 &  FS1 &  FS0;

/* When the input clock address doesn't match the current clock address,
   it's time for a change.  Change must occur when PCLK = FCLK is high, 
   so we have enough time to wrap around and assert the CHANGING output. */

CHANGE		= (LS2 $ FS2) & FCLKOUT & !RST
		# (LS1 $ FS1) & FCLKOUT & !RST
		# (LS0 $ FS0) & FCLKOUT & !RST
		# CHANGE & !CHANGING & !RST;

/* The new clock can be enabled once we're in changing mode and on the
   right half of SCLK.  */

NEWCLK		= CHANGING & SCLK   & !RST
		# CHANGING & NEWCLK & !RST;

/* Once a change is called for, we need to set the CHANGING indicator.  This
   goes valid on the rising edge of the FCLK, which at this time is synched
   to the PCLK.  Once CHANGING is indicated, PCLK is forced high.  Since
   CHANGING only takes place on PCLK going high, no slivers happen upon
   entering the change cycle. 

CHANGING.D	= CHANGE
		# CHANGING & !NEWCLK;
CHANGING.AR	= RST;

/* These are the latched clock selects.  They remain constant until we're
   in changing mode, at which point the new clock address can come
   through. */

LS0.D		=  CHANGING & FS0
		# !CHANGING & LS0;
LS1.D		=  CHANGING & FS1
		# !CHANGING & LS1;
LS2.D		=  CHANGING & FS2
		# !CHANGING & LS0;
[LS3..0].AR	= RST;