PARTNO		U120 ;
		NAME		U120 ;
		DATE		November 19, 1992 ;
		REV		1 ;
		DESIGNER	Dave Haynie ;
		COMPANY		Commodore ;
		ASSEMBLY	Nyx ;
		LOCATION	West Chester ;
		DEVICE		g22V10 ;

/************************************************************************/
/*									*/
/*	Nyx	Basic clock generator					*/
/*									*/
/*	This device generates the simple system clocks which derive	*/
/*	from the AAA bus basis clock, and manages the various genlock	*/
/* 	type clocks. 							*/
/*									*/
/************************************************************************/
/*									*/
/* DEVICE DATA:								*/
/*									*/
/*	Device:		22V10-10					*/
/*	Clock:		57MHz						*/
/*	Unused:		8(I),9(I),10(I),11(I),13(I)			*/
/*									*/
/************************************************************************/
/*									*/
/* REVISION HISTORY:							*/
/*									*/
/*	DBH Oct 10:	Original version.				*/
/*	DBH Nov 19:	Added power-on reset to force clocks into the	*/
/*			correct phasing.				*/
/*									*/
/************************************************************************/

/** INPUTS: **/

PIN 1		=  C57M		;	/* 57MHz basis clock */
PIN 2		= !CAPEN	;	/* Capture clock enable */
PIN 3		=  CAPC		;	/* Capture clock */
PIN 4		= !IGENEN	;	/* Internal genlock clock enable */
PIN 5		=  IGENC	;	/* Internal genlock clock */
PIN 6		= !XGENEN	;	/* External genlock clock enable */
PIN 7		=  XGENC	;	/* External genlock clock */
PIN 8		= !PRST		;	/* Power-on reset. */

/** OUTPUTS: **/


PIN 14		= !CDAC		;	/* 7.16MHz 90 degree clock */
PIN 15		=  C7M		;	/* 7.16MHz primary clock */
PIN 16		= !C4		;	/* 3.56MHz quad phase 4 */
PIN 17		=  C3		;	/* 3.56MHz quad phase 3 */
PIN 18		=  C2		;	/* 3.56MHz quad phase 2 */
PIN 19		=  C1		;	/* 3.56MHz quad phase 1 */
PIN 20		=  C14M		;	/* 14MHz clock */
PIN 21		=  C28M		;	/* 28MHz clock */
PIN 22		= !XCLKEN	;	/* Selected external clock enable */
PIN 23		=  XCLK		;	/* Selected external clock source */

/** OUTPUT TERMS: **/

/* The 28MHz clock is a simple divide down. */

C28M.D		= !C28M;

/* The 14MHz clock derives from the both higher clocks. */

C14M.D		= !C28M & !C14M
		#  C28M &  C14M;

/* The 7MHz clocks go similarly.  Care is taken here to make
   sure that the CDAC clock trails the C7M clock no matter
   what the power-up state of each clock is. */

C7M.D		= !C28M & !C14M & !C7M
		#          C14M &  C7M
		#  C28M &          C7M;

CDAC.D		= !C28M &  C14M & C7M
		#         !C14M & CDAC
		#  C28M &         CDAC;

/* And strangely enough, the 3.5MHz clocks are generated the
   same basic way, with interlocks to assure proper phasing. */

C1.D		= !C28M & !C14M &  !C7M & !C1
		#                   C7M &  C1
		#          C14M &          C1
		#  C28M &                  C1;

C2.D		= !C28M &  C14M &   C7M &  C1
		#                  CDAC &  C2
		#         !C14M &          C2
		#  C28M &                  C2;

C3.D		= !C28M & !C14M &   C7M &  C1
		#                  !C7M &  C3
		#          C14M &          C3
		#  C28M &                  C3;

C4.D		= !C28M &  C14M &  !C7M &  C1
		#                 !CDAC &  C4
		#         !C14M &          C4
		#  C28M &                  C4;

[C1..4].AR	= PRST;

/* The external clock enable is a composite of any of the
   enables. */

XCLKEN		= CAPEN
		# XGENEN
		# IGENEN;

/* The genlock clocks are prioritized here to ensure only
   one drives the system at a time.  The priority sets up
   capture as the highest, since any capture board should be
   capable of going away when captures are not occuring.
   External genlock overriding internal genlock allows both
   to be occasionaly used in a system without the need to
   necessarily dismantle it (assuming the internal Genlock
   doesn't go nuts when the external is driving. */

XCLK		=  CAPC & CAPEN
		# XGENC & XGENEN & !CAPEN
		# IGENC & IGENEN & !CAPEN & !XGENEN;