PARTNO		U104 ;
		NAME		U104 ;
		DATE		March 18, 1992 ;
		REV		4 ;
		DESIGNER	Dave Haynie ;
		COMPANY		Commodore ;
		ASSEMBLY	Nyx ;
		LOCATION	West Chester ;
		DEVICE		g22V10 ;

/************************************************************************/
/*									*/
/*	Nyx	AAA Interface						*/
/*									*/
/*	This device is the basic interface to the AAA chip set.  It	*/
/*	generates chip selects for AAA, termination for the '030 bus.	*/
/*									*/
/************************************************************************/
/*									*/
/* DEVICE DATA:								*/
/*									*/
/*	Device:		22V10-10					*/
/*	Clock:		BUSCLK						*/
/*	Unused:		NONE						*/
/*									*/
/************************************************************************/
/*									*/
/* REVISION HISTORY:							*/
/*									*/
/*	DBH Oct 10:	Original version.				*/
/*	DBH Feb 10:	DSACKs were driving all the time, now properly	*/
/*			qualified with NEED.				*/
/*	DBH Mar 18:	NEED timing is wrong, it cuts off when we get	*/
/*			a CGRANT, so as not to allocate the next	*/
/*			cycle.  ACS replaces NEED for qualifier.	*/
/*	DBH Mar 18:	CBLT polarity is reversed -- the Bridgette	*/
/*			chip takes an active-low latch, since its	*/
/*			latching signal in the A4000 is just DSACK1.	*/
/*	DBH Mar 18:	Change CBLT/DSACK timing, see notes.		*/
/*	DBH Mar 18:	OECD* was being asserted too late for writes,	*/
/*			which are early writes, so data must be valid	*/
/*			on the bus before CAS.  See notes.		*/
/************************************************************************/

/** INPUTS: **/

PIN 1		=  BUSCLK	;	/* CIA latching signal */
PIN 2		= !CGRANT	;	/* Chip bus cycle grant. */
PIN 3		= !AS		;	/* '030 Address strobe. */
PIN 4		=  LATCH	;	/* Andrea latch control */
PIN 5		= !CREG16	;	/* 16-bit register decode */
PIN 6		= !CREG32	;	/* 32-bit register decode */
PIN 7		= !CRAMADDR	;	/* Chip RAM address */
PIN 8		=  RW		;	/* '030 data direction */
PIN 9		= !ALE		;	/* Chip bus address latch enable */
PIN 10		=  FC0		;	/* Function codes */
PIN 11		=  FC1		;
PIN 13		=  FC2		;

/** OUTPUTS: **/

PIN 14		= !DSACK0	;	/* '030 bus termination */
PIN 15		= !DSACK1	;
PIN 16		= !CIIN		;	/* '030 bus cache inhibit */
PIN 19		= !ACS		;	/* Andrea chip select (AS) */
PIN 20		= !CBLT		;	/* Chip bus data latch */
PIN 21		= !OECD		;	/* Chip bus data enable */
PIN 22		= !REG_RAM	;	/* Register or RAM? */
PIN 23		= !NEED		;	/* Chip bus request */

/** USED INTERNALLY: */

PIN 17		= !MINE		;	/* Grant latched though end */
PIN 18		= !DONE		;	/* Beginning of the end. */

/** INTERNAL TERMS: **/

/* Valid processor access space? */

/* Some basic decodes. */

cycqual		= AS & (FC1 $ FC2);

access		= CREG16
		# CREG32
		# CRAMADDR;

/** OUTPUT TERMS: **/

/* This is the chip access request.  This is drive to Andrea 
   asynchronously, and must lead ACS.  Once a grant is received,
   NEED is negated so as not to request the next chip bus 
   cycle. */

NEED		= !ACS & cycqual & access
		# NEED & !CGRANT;

/* This is a basic address strobe for Andrea, driven asynchronously
   to Andrea following NEED.  This could be driven continuously,
   rather than qualified by an actual access, as the 680x0 AS* would
   be.  It's driven this way to ensure that NEED to AS timing is
   possible even in the rather kludgy logic the Nyx system used to
   get its chip selects. */

ACS		= cycqual & access & NEED
		# cycqual & access & ACS;

/* This indicates to Andrea if the cycle is going to be to Chip RAM or
   to Chip register space.  This must be valid prior to ACS and held
   through CGRANT negated.  Since CRAMADDR is the faster decode, I use
   it and make the RAM case the active case, register the default. */

REG_RAM		= CRAMADDR
		# REG_RAM & CGRANT;

/* This is asserted to disable the data cache for all accesses to either
   Chip RAM or registers. */

CIIN		= cycqual & access & FC0;
CIIN.OE		= ACS;

/* Hold on to the idea that we have the chip bus. */

MINE		= ACS & CGRANT
		#  AS & MINE;

/* Mark the LATCH transition from high to low.  We need
   this to detect the low to high transition elsewhere. */

DONE		= MINE & !LATCH
		#   AS & DONE;

/* The data is asynchronously acknowledged.  The memory region determines
   the port size -- as long as it's not CREG16, we have a 32-bit port.  */

DSACK0		= MINE & DONE & LATCH & !CREG16
		#   AS & DSACK0;

DSACK1		= MINE & DONE & LATCH
		#   AS & DSACK1;

[DSACK1..0].OE	= ACS;

/* We're counting on the LATCH signal to know what its doing, at least at
   present, in this version of the control logic.  In theory, the LATCH
   signal rises when data is valid.  Of course, we naturally need an
   active low latch, so CBLT is driven from LATCH. */

CBLT		= MINE & DONE & LATCH
		#   AS & CBLT;

/* The data output enable depends on what we're doing.  It can't be driven
   onto the chip bus until chip addresses are done with, it can't be driven
   onto the 68030 bus until we're safely selected.  For reads, the data is
   held on the '030 bus until the '030 cycle actually ends.   

   For writes, I originally clocked out OECD based on a receipt of CGRANT 
   and ALE.  That isn't going to work, since ALE is driven from the rising 
   edge of the bus clock too, and CAS from the next rising edge, where 
   data must be valid.  I don't like it, but I seem to have no choice but
   to drive OECD directly off ALE to get data set up to CAS.  It looks like
   you might be able to do something more reasonable with a state machine
   that runs off MCLK. */

OECD		=  RW & MINE 
		#  RW & OECD & AS
		# !RW & MINE & ALE;