PARTNO U103 ; NAME U103 ; DATE October 10, 1992 ; REV 0 ; DESIGNER Dave Haynie ; COMPANY Commodore ; ASSEMBLY Nyx ; LOCATION West Chester ; DEVICE g22V10 ; /************************************************************************/ /* */ /* Nyx Chip register decoder, CIA address latch */ /* */ /* This device does full decoding for the two chip register */ /* spaces, and it latches the CIA address/control signals. */ /* */ /************************************************************************/ /* */ /* DEVICE DATA: */ /* */ /* Device: 22V10-10 */ /* Clock: LATCH_ADR */ /* Unused: 19(I/O) */ /* */ /************************************************************************/ /* */ /* REVISION HISTORY: */ /* */ /* DBH Oct 10: Original version. */ /* */ /************************************************************************/ /** INPUTS: **/ PIN 1 = LATCH ; /* CIA latching signal */ PIN 2 = RW ; /* Bus data direction */ PIN 3 = !NEWIO ; /* Pre-decode chip select */ PIN [4..6] = [A18..16] ; /* Bus address */ PIN [7..10] = [A11..8] ; PIN 11 = A3 ; PIN 13 = A2 ; /** OUTPUTS: **/ PIN 14 = CA2 ; /* CIA addresses. */ PIN 15 = CA3 ; PIN 16 = CRW ; /* CIA data direction */ PIN 17 = !CREG32 ; /* 32-bit Chip register decode */ PIN 18 = !CREG16 ; /* 16-bit Chip register decode */ PIN [20..23] = [CA8..11] ; /* More CIA addresses. */ /** INTERNAL TERMS: **/ /* Valid processor access space? */ /* Some basic decodes. */ chipreg = NEWIO & A18 & A17 & A16; /** OUTPUT TERMS: **/ /* These are the decodes for chip register space. The 16-bit registers are located at $00DFF000-$00DFF1FF, the 32-bit registers at $00DFF200- $00DFFFFF. The incoming NEWIO strobe decodes A31..A19 of this address, the rest happens here. */ CREG32 = chipreg & A11 # chipreg & A10 # chipreg & A9; CREG16 = chipreg & !A11 & !A10 & !A9; /* All the CIA stuff gets latched by the LATCH term. */ CRW.D = RW; CA2.D = A2; CA3.D = A3; CA8.D = A8; CA9.D = A9; CA10.D = A10; CA11.D = A11;